A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

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作者： Bilal I,Abdulrazzaq ^[1] ; Izhal,Abdul Halin ^[2] ; Shoji,Kawahito ^[3] ; Roslina M,Sidek ^[2] ; Suhaidi,Shafie ^[2] ; Nurul Amziah Md,Yunus ^[2]

作者单位： Department of Electrical and Electronic Engineering, Universiti Putra Malaysia (UPM), 43400 Serdang, Selangor Malaysia ; Department of Electronic and Communications Engineering, Al-Nahrain University, Al-Jadriya Complex, Baghdad, 10070 Iraq. ^[1] Department of Electrical and Electronic Engineering, Universiti Putra Malaysia (UPM), 43400 Serdang, Selangor Malaysia. ^[2] Imaging Devices Laboratory, Research Institute of Electronics, Shizuoka University, 3-5-1 Johoku, Nakaku, Hamamatsu, Shizuoka 432-8011 Japan. ^[3]

关键词 Delay element Delay line Delay range Delay resolution Delay-locked loop (DLL)Jitter Linearity

DOI 10.1186/s40064-016-2090-z

PMID 27104122

发布时间 2020-10-01

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A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

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A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

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