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Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller.

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第一作者： Run-Ze,Yu

第一单位： School of Integrated Circuits, Huazhong University of Science and Technology, Wuhan 430074, China.

作者： Run-Ze,Yu ^[1] ; Zhen-Hao,Li ^[1] ; Xi,Deng ^[1] ; Zheng-Lin,Liu ^[1]

作者单位： School of Integrated Circuits, Huazhong University of Science and Technology, Wuhan 430074, China. ^[1]

关键词 dynamic voltage scaling (DVS)error detection and correction (EDaC)error-aware capability high stability near-threshold operation negative design margin ultra-low voltage

DOI 10.3390/s23177498

PMID 37687954

发布时间 2023-09-11

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Sensors (Basel, Switzerland)

2023年23卷17期

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Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller.

Sensors (Basel, Switzerland)

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Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller.

Sensors (Basel, Switzerland)

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Sensors (Basel, Switzerland)

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